For the development of demanding high complex digital and mixed-signal circuits with advanced requirements in chiplet design in nanometer silicon technologies a communication IP pool with PHYs (physical layer hard-IPs) will be needed by Fraunhofer matching and complementing the communication standards like PCIe, UCIe and further available SERDES IPs (SERializer-DESerializer). As well a configurable NoC IP (Network on Chip) will be need for intra-chip communication.